The present invention relates generally to data transmission systems and more particularly relates to a system for synchronizing data transmission between two computers, ICs, interboard connections or between other types of data interfaces in a data transmission system.
In numerous data links in which digital data is transmitted between ICs, printed circuit boards or computers, a specific synchronization pattern or sequence is added to the leading end or to both the leading and trailing ends of each block of data, e.g., cell, packet, frame, etc., in order to provide synchronization. Particularly, where the packets are variable in length, reliable detection of the delimiter is necessary for the recognition of the leading and trailing packet ends.
In parallel digital data transmission, the parallel data is often converted using time division multiplexing into a serial signal for transmission of the data on a reduced number of data lines. In such a data transmission system, the receiving side must achieve cell or frame synchronization for the serial-to-parallel conversion in order to ensure that the parallel data input on the transmitting side and the parallel data output on the receiving side are in sync with one another. To realize synchronization, a specific synchronization pattern is typically used which enables the receiving side to achieve synchronization.
In addition, there may be a problem where the same pattern as the synchronization sequence is present in the data and can be erroneously judged to be the synchronization pattern. A second problem that may arise in the data link is that of transmission time differences or skews from one cell or packet to the next. In the case of transmitting parallel data after the parallel-to-serial conversion, there is a requirement for synchronization on the receiving side. For the restoration to the original parallel data it is necessary to discriminate each cell or packet after the serial-to-parallel conversion. Some form of correction must be provided to align the data being received with a cell or packet boundary. This requires a certain period of time. It is desirable to make this time as small as possible since during this time, no data can be transmitted. A synchronization sequence can be used but this causes a reduction in the transmission bandwidth. Thus, it is desirable to have a synchronization sequence that causes a minimum reduction in transmission bandwidth in terms of the number of bits required but yet enables the receiver to properly sync up with the transmitter.
The present invention is an apparatus and method for providing synchronization in a data transmission system. The invention is applicable in numerous situations where data is transmitted from one point to another in blocks of data such as cells, packets, frames, etc. The invention is described in the context of circuitry suitable for use in transmitting ATM/Ethernet cells between modules on a PCB. The data is transmitted over one or more differential lines along with a clock signal. Note, however, that the invention is suitable in numerous other applications, as would be obvious to one skilled in the art.
The invention achieves synchronization via the use of a short synchronization sequence that is inserted in the header of the cell to be transmitted. The conventional 5 byte ATM header of the cell is stripped off and a 4-byte header is used in its place. A 2-bit sync sequence is inserted at the beginning of the header. At the receiving end, a pair of state machines search for and track the sync sequence. A feedback signal is generated that is used by the receiver to adjust its framing in order to align the received data with the boundaries of the cells.
To aid in detecting the sync sequence, the sync bits are rotated each cell cycle in the following cyclical fashion: 00, 01, 10, 11. The sync sequence is cycled and transmitted with each cell. To avoid confusion with data in the cell that mimics the sync sequence and to minimize the synchronization time, the remote transmitter transmits special idle cells that contain all ones except for the 2-bit sync sequence field during the period that the adjacent receiver is attempting to sync up with the remote transmitter.
Thus, if the receiver on side A is not synchronized, for example, it will make sure that the receiver on side B is synchronized by sending special sync cells. If the receiver on side B is already synchronized, the special sync cells cause the transmitter on side B to send a special cell that assists the receiver on side A to synchronize.
There is provided in accordance with the present invention, in a bidirectional data transmission system, including a first and second side, each side including a transmitter and a receiver, a method of synchronizing the transmission of blocks of data from transmitter to receiver in both directions, the method comprising the steps of inserting a synchronization field into a header preceding the block of data, cycling the value of the synchronization field wherein the synchronization field is cycled once for each block of data to be transmitted, transmitting idle sync cells during the time the receiver attempts to synchronize with the transmitter, transmitting, by a transmitter on the first side, idle sync answer cells in response to the receiver on the first side receiving idle sync cells from the transmitter on the second side, searching, on the receiver, for the cycle synchronization sequence and adjusting the framing of the data received by the receiver in the event the synchronization sequence is not found within a predetermined period of time.
The synchronization field comprises two bits and is cycled through the pattern: 00, 01, 10, 11 and the block of data comprises an Asynchronous Transfer Mode (ATM) 48 byte cell payload. The idle block comprises all one except for the synchronization field. The step of synchronizing comprises the step of providing a count state machine and a sync state machine to search for and track the cycling of the synchronization field sequence. The period of time comprises a multiple number of cell times wherein each cell comprises 48 bytes.
There is also provided in accordance with the present invention an apparatus for synchronizing the transmission of blocks of data comprising a transmitter comprising means for generating a synchronization field to be inserted into a header that is transmitted preceding the block of data, the synchronization field cycled once for each block of data transmitted, means for transmitting an idle block of data during attempts to synchronize the transmission of the blocks of data, a receiver comprising means for searching a received data stream for the cyclic synchronization sequence and means for adjusting the framing of data received by the receiver in the event the synchronization sequence is not found within a predetermined period of time.